Planar void free isolation structure

ABSTRACT

A void-free isolated semiconductor substrate is described which contains a pattern of substantially vertically sided trenches within a semiconductor body. The pattern of isolation trenches isolate regions of monocrystalline semiconductor material which may contain active and passive semiconductor devices. A first insulating layer is located upon the sidewalls of the trenches. The base or bottom of the trenches is open to the monocrystalline semiconductor body. An epitaxial layer extending from the base of the trenches fills the pattern of trenches up to a level from the upper surface of the trenches as specified approximately by the equation: 
     
         y=0.34x 
    
     where y is the distance between the epitaxial layer and the top surface and x is the trench width. The preferred range for the trench width x is about 10 micrometers or less. A polycrystalline silicon layer fills the additional portion of the pattern of trenches above the upper surfaces of the epitaxial layer. A second insulating layer is located on the polycrystalline silicon layer within the trenches for isolation of the pattern of trenches from the ambient. It is the dense epitaxial monocrystalline semiconductor which prevents the formation of voids within the pattern of trenches. The polycrystalline silicon layer above the epitaxial layer completely covers the undesirable sharp faceted structure at the top of the epitaxial semiconductor growth structure.

This is a division of Ser. No. 624,425, filed June 24, 1984, now U.S.Pat. No. 4,528,047.

DESCRIPTION FIELD OF THE INVENTION

The present invention is concerned with methods for filling trenches insemiconductor substrates so as to form void free patterns of isolationwithin the substrate. In particular, the process and resulting structureis involved in forming a pattern of isolation is a semiconductorsubstrate wherein the isolation includes epitaxial semiconductormaterial and polycrystalline silicon material.

CROSS REFERENCE TO RELATED APPLICATION

Patent application Ser. No. 624,320, filed June 25, 1984, entitled"Method for Forming a Void Free Isolation Pattern and ResultingStructure", by V. J. Silvestri et al.

DESCRIPTION OF THE PRIOR ART

In the monolithic integrated circuit technology, it is usually necessaryto isolate various active and passive elements from one another withinthe integrated circuit structure. These devices have been isolated byback biasing PN junctions, partial dielectric isolation and completedielectric isolation. The dielectric materials used have been silicondioxide and the like. The preferred isolation for these active andpassive devices is some form of dielectric isolation. The dielectricisolation has the substantial advantage over PN junction isolationbecause it allows the butting of circuit elements against the isolationand thereby result in greater density of packing of the active andpassive devices in the integrated circuitry.

A form of dielectric isolation is disclosed in the H. B. Pogge U.S. Pat.No. 4,256,514. Pogge describes isolation refill techniques employed indeep trench isolation formation wherein chemical vapor deposition or thelike is used to deposit insulating material such as, silicon dioxide orpolycrystalline silicon into the pattern of trenches. Such systemsinvolve a homogeneous gas phase reaction wherein the silicon dioxide,polycrystalline silicon or the like is formed in the gas from thereactive species present and is deposited therefrom onto the surfacesand into the pattern of trenches. The problem with this method ofdeposition is that there is a tendency to form voids within the trenchpatterns particularly where trenches cross one another. Also, therefilling deposition can produce structurally deficient or looselypacked material which may not be the best isolation structures inintegrated circuits. The presence of voids and this loose structure havea tendency to magnify the formation of defects in silicon areas whichare later to serve as active or passive device regions.

The L. M. Ephrath et al., Patent Application Ser. No. 393,997 filed June30, 1982 assigned to the same assignee as the present inventiondescribes another dielectric isolation method and resulting structurewherein the pattern of trenches is filled with void-free polycrystallinesilicon or epitaxial silicon. Ephrath et al., utilize a sidewallcomposed of insulating material with or without a nucleating materialthereover. The bottom of the trench pattern is open to themonocrystalline semiconductor body such as silicon. Epitaxial silicon isthen grown from the bottom opening to the monocrystalline silicon bodyand perpendicular from the sidewall surfaces containing the nucleatingmaterial. While the result of this epitaxial growth is a voidfree-structure, there are sharp grooves near the top of the insulatingsidewall, as seen in the FIG. 1 drawing, where the insulating sidewallis silicon dioxide layer 1 and silicon nitride layer 2 and no nucleatingmaterial is used. The epitaxial layer filling 3 grows from the substrate4. The epitaxial layer and substrate is typically monocrystallinesilicon. This is also illustrated in N. Endo et al., "Novel DeviceIsolation Technology with Selective Epitaxial Growth" IEDM Tech. Digestp. 241, San Francisco Meeting Dec. 13-15, 1982. Where a nucleating layer5 of, for example, polycrystalline silicon is used over the insulatingsidewall 1, 2 only a small epitaxial layer filling 6 and mostlypolycrystalline semiconductor layer 7 results as seen in FIG. 2. A void8 is usually formed in the structure particularly where the trench isdeep such as 3 to 6 micrometers or more.

SUMMARY OF THE PRESENT INVENTION

The void-free isolated semiconductor substrate is described whichcontains a pattern of substantially vertically sided trenches within asemiconductor body. The pattern of isolation trenches isolate regions ofmonocrystalline semiconductor material which may contain active andpassive semiconductor devices. A first insulating layer is located uponthe sidewalls of the trenches. The base or bottom of the trenches isopen to the monocrystalline semiconductor body. An epitaxial layerextending from the base of the trenches fills the pattern of trenches upto a level from the upper surface of the trenches as specifiedapproximately by the equation:

    y=0.34x

where y is the distance between the epitaxial layer and the top surfaceand x is the trench width.

The preferred range for the trench width x is about 10 micrometers orless. A polycrystalline silicon layer fills the additional portion ofthe pattern of trenches above the upper surfaces of the epitaxial layer.A second insulating layer is located on the polycrystalline siliconlayer within the trenches for isolation of the pattern of trenches fromthe ambient. A polycrystalline silicon nucleating layer may also belocated upon the sidewalls above epitaxial silicon filling and on theepitaxial silicon upper portion to assure the growth of a dense, evenlygrown polysilicon layer in the pattern of trenches. It is the denseepitaxial monocrystalline semiconductor which prevents the formation ofvoids within the pattern of trenches. The polycrystalline silicon layerabove the epitaxial layer completely covers the undesirable sharpfaceted structure at the top of the epitaxial semiconductor growthstructure.

The methods for forming void-free isolation pattern structure in asemiconductor body such as, monocrystalline silicon proceeds by firstforming substantially vertically sided pattern of trenches having aninsulating layer sidewall and open bottom to the monocrystalline siliconbody. Monocrystalline silicon is epitaxially grown in the trenches fromthe monocrystalline silicon bottom to form a dense voidfree trenchstructure up to a level specified approximately by the equation:

    y=0.34x

where y is the distance between the epitaxial layer and the top surfaceand x is the trench width. The upper surfaces of the epitaxial grownlayer forms an objectionable sharp grooved or faceted structure with theinsulating layer sidewall. Polycrystalline silicon is formed over thesurfaces of the trench to completely cover this objectionable sharpfaceted structure. The polycrystalline silicon layer is removed fromareas above the pattern of trenches by a known planarization techniques.A passivation layer such as, silicon dioxide may be utilized to isolatethe pattern of trenches from the ambient. This may be accomplished bythe thermal oxidation of the polycrystalline silicon at a suitabletemperature to form a silicon dioxide layer on the polycrystallinesilicon layer in the pattern of trenches.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a prior art filled trench structure which has beenformed using the epitaxial growth of semiconductor material.

FIG. 2 is a prior art illustration of a trench which has been filledusing the polycrystalline silicon.

FIGS. 3 through 6 illustrate the process of the present invention forforming a void-free isolation structure in a monocrystallinesemiconductor body.

FIG. 7 illustrates the problem and solution of filling the top portionof the pattern of trenches with polycrystalline silicon while notcausing void formation.

FIG. 8 is a graphical representation showing the relationship ofvoid-free filling versus trench width.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring now more particularly to FIG. 3, there is shown asemiconductor body 12 of a P-conductivity type. The semiconductor bodyis typically <100> crystallographically oriented silicon and of aresistivity in the order of 1 to 20 ohm-cm. Conventional lithography andetching techniques are utilized to form the mask for the subcollectordiffusion step. N type impurities are then diffused by conventionaltechniques to form a region having a surface concentration level oftypically 5×10²⁰ atoms/cc. The N type impurity may be, for example,arsenic or antimony. The structure is now subjected to a thermaloxidation to form silicon dioxide thereover. Simultaneously with thegrowth of the silicon dioxide, the N type impurity is driven furtherinto the semiconductor body. If it were desired to form a PNP transistorrather than an NPN transistor, opposite conductivity types are utilizedas is well understood by those skilled in the art.

The silicon dioxide layer on the surface of the silicon body is removedby use of conventional etching techniques. The silicon body is thenplaced in an epitaxial growth chamber and a monocrystalline siliconlayer is grown upon the principal surface of the silicon body having theN+ diffusions therein. This growth is done by conventional techniquessuch as the use of SiCl₄ /H₂, SiH₂ Cl₂ /H₂ or SiH₄ /H₂ mixtures atgrowth temperatures of about 1000° C. to 1200° C. The thickness of theepitaxial layer is typically 1.5 micrometers but may be in the range of0.5 to 5 micrometers. During the epitaxial growth the epitaxial layer isdoped with an N- type impurity of a low concentration level which istypically 2×10¹⁶ atoms/cc. During the epitaxial growth, the N+ regionoutdiffuses into the epitaxial layer to fully form the final N+ region14 as illustrated in FIG. 3. The remaining portions of the epitaxiallayer 16 will be N- doped. The region 14 will be connected as thesubcollector of the NPN transistor as is understood by those skilled inthe art.

Silicon dioxide layer 20 is formed by conventional techniques of eitherthermal growth at a temperature of about 970° C. in wet or dry oxygenambient or by chemical vapor deposition. The silicon nitride layer 22 isformed thereover typically by a chemical vapor deposition. A secondsilicon dioxide layer 24 is formed by chemical vapor deposition over thesilicon nitride layer 22. A resist layer (not shown) is deposited overlayer 24.

This layer is then formed into a mask using conventional lithographytechniques so that openings are provided in the desired pattern ofisolation trenches planned. The layers 20, 22 and 24 are etched usingconventional chemical, reactive ion etching or plasma etching techniquesat the openings of resist layer down to the monocrystalline siliconsubstrate.

The substrate is now ready to utilize the layers 20, 22, 24 as the maskfor the trench formation following the removal of the resist layer fromthe surface of layer 24. This process must be accomplished usinganisotropic reactive ion etching (RIE) which produces substantiallyvertical sidewalls for the trenches. The trench depth for bipolar deviceisolation is at least 3 and preferably 4 to 7. One suitable example offorming the trenches by RIE is the use of carbontetrafluoride (CF₄) gas.Other suitable examples of gases include CCl₄ -Ar and Cl₂ -Ar. Detailsof the RIE are described in the co-pending patent application of J. M.Harvilchuck et al., Ser. No. 960,322, filed Nov. 13, 1978, which is acontinuation of patent application Ser. No. 822,775, filed Aug. 8, 1975,now abandoned and the J. A. Bondur et al., U.S. Pat. No. 4,104,086 andassigned to the same assignee as the assignee of this invention.

An insulator layer 28 of, for example, silicon dioxide is preferablyformed by thermal oxidation in steam at a temperature of about 970° C.on the surface of the trenches. The layer 28 of silicon dioxide mayalternatively be formed by chemical vapor deposition but this wouldnecessitate the removal of the deposited silicon dioxide from the layer24 surface. The preferred thickness of the layer 28 of the silicondioxide is preferably in the range of 30 to 100 nanometers. It is alsodesirable to form a silicon nitride layer 30 on the surface of thissilicon dioxide layer 28 to improve the isolation properties of thesidewall. This silicon nitride layer can be deposited by conventionalchemical vapor deposition techniques. This nitride thickness should bebetween about 30 to 100 nanometers to prevent defect formation. Anadditional layer 21 of silicon dioxide is preferrably deposited on thesilicon nitride layer for the subsequent partial epitaxial refill step.This silicon dioxide layer 31 can be as thin as 50 to 500 nanometers. Itcan be deposited by LPCVD techniques using a reactant such as TEOS.

The layers 28, 30 and 31 are removed from the base of the trench patternby reactive ion etching. The result of the process is shown in FIG. 3.

Next, monocrystalline semiconductor material, typically silicon isepitaxially grown in the pattern of trenches from the monocrystallinesemiconductor bottom of the trench. The method of growing silicon is bya gas-solid or heterogeneous reaction system. The heterogeneous reactionsystem desirably includes hydrogen, silicon and chlorine. Theparticularly preferred system is a combination of gases including SiCl₄,H₂ and the P+ dopant B₂ H₆ with an HCl injection as described in thecross-referenced patent application above. The epitaxial growth trenchfilling process is carried out at temperature of between about 900° C.to 1100° C. and preferably about 1000° C. to provide a sufficiently fastfilling of the trenches. The preferred rate is between 0.07-0.2μm/minute. This is highly preferrable when a bipolar pattern of trenchisolation is being formed, because of the substantial depth of thetrenches. The dopant concentration of B₂ H₆ or the like is between about5×10¹⁷ to 5×10²⁰ to provide a epitaxial filling material having aresistivity of about 0.1 to 0.0006 ohm-cm. Subsequent heating of thisstructure produces a P+ region 42 in the substrate to form one portionof the isolation structure. The trench widths on the same integratedcircuit substrate may be of various widths in the range of, for example,1 to 300 micrometers. Experiments have shown that the re-filling levelof epitaxial silicon does not vary significantly for trench widths inthis range with a experimental maximum deviation to be about ±10%.Re-fills using this system contain no voids and exhibited top growthsurfaces indicative of highly-oriented single crystal growth.

The epitaxial layer extends from the base of the pattern of trenches upto between about 0.3 to 4 micrometers or more from the upper top surfaceof the pattern of trenches. The 0.34 case is where the trench width isabout 1 micrometer and 3.4 is where the trench width is 10 micrometers.The equation y=0.34 x applies where y is the distance between theepitaxial layer and the top surface and x is the trench width. Thepreferred range of trench width is less than about 10 micrometers. Thecriteria for the height of this epitaxial fill in the trench is basedupon the cross-section of the trench so that no void occurs during thesubsequent deposition of the polycrystalline silicon filling material.The consideration and details of this problem will be consideredsubsequently when FIGS. 7 and 8 are considered in detail. The depth ofthe trench is not an important consideration in deciding what portion ofthe trench should be left for the final polysilicon refill. This is dueto the nature of the growth stages to be described in relation to FIG. 8below. A nucleating layer 44 is deposited over the exposed epitaxialsurface as seen in FIG. 3 so that the upper surface of the epitaxiallayer 40, the presently exposed sidewall of the pattern of trenches andthe upper surface of layer 24 are covered with this nucleating layer 44.The nucleating layer is preferably used and is composed ofpolycrystalline silicon to produce a uniform growth from the surface ata given growth rate. It is very important that this uniform growth isobtained so that the subsequent chemically-mechanically polishingprocess is effective in removing the subsequent polycrystalline siliconlayer from the surface 24. The preferred process for laying down thisnucleating layer involves deposition of polysilicon in a LPCVD systememploying SiH₄ at 650° C. to a thickness of between 100 to 300nanometers. The preferred amount being 200 nanometers.

The next step is to deposit a polycrystalline silicon layer 46 as seenin FIG. 4 to completely fill the pattern of trenches without forming anyvoids within the structure. A polysilicon layer 46 is nowchemically-mechanically polished using a 3 weight percent SiO₂ slurry inH₂ O adjusted to pH=11.8. The polishing is carried out at 16 psi fordesired time. A poromeric polishing pad is used to rotatably pressagainst the wafers being polished at the 16 pSi causing the removal ofelevated portions of the polysilicon layer. The mechanism of the processis not fully understood, but it is believed that the surface of thepolysilicon is hydrolyzed by the slurry and it is this softer materialwhich is polished of by action of the SiO₂ slurry and the polishing pad.

Plasma etching or the like may be now utilized to remove a portion ofthe polycrystalline silicon from the pattern of the trenches so as toproduce the structure shown in FIG. 5. A silicon dioxide capping layermay now be formed by thermal oxidation of the polycrystalline siliconlayer 46. The resulting capping layer is shown at FIG. 6 as layer 48.

FIG. 7 schematically illustrates the problem of forming a conformallayer of polycrystalline silicon over the epitaxial silicon partiallyfilled trench. FIG. 8 is a plot of refill level vs. trench widthobserved for five polysilicon refill experiments which employeddifferent times. The detailed experiments are given in the EXAMPLES Ithrough V below. Trenches of different widths were formed on a siliconsubstrate such that they would be filled to differing levels. Scanningelectron microscope photos were taken of cleaved cross-sections of thetrench and refill. Measurements were taken from the photos to obtain thedata shown in FIG. 8 and TABLES I-V. In FIG. 8 schematic drawings of theimportant growth stages of refill observed are depicted in the insertaccompanying the data described further below in more detail.

To accomplish elimination of voids in the polysilicon refill it isimportnat to remain in the conformal growth regime as defined in FIG. 8.This regime includes conditions that include that portion of the plotbelow the line 50 drawn through the data and zero. This line 50 can beexpressed by the linear equation y=0.34 x where y is the "refill level"at which the first void could possibly form and x is the "trench width".Voids can form when the sidewall growth meets at the bottom of thetrench to form an initial cusp or steep V-shaped refill. Refill ratesare observed to increase sharply at this point of initial meeting ofsidewall surfaces. Rates can be obtained from FIG. 8 by dividing therefill level achieved for each data set by the time associated with theexperiment indicated in the key. The key being: curve 60=3.3 minutes;curve 62=5 minutes; curve 64=6.6 minutes; curve 66=10 minutes; and curve68=15 minutes. It is in this final closure stage that voids can form.The voids result when slightly unmatched surfaces meet, join and preventdeposition gases further access. Voids observed are of the order ofpolysilicon crystallite (about 200 nanometers or less) which make up thewall irregularities, and are observed to occur randomly along a seamaligned with a cusp. This cusp runs centrally in trenches. Thesedepressions can be more pronounced at trench intersections and cornerswhere the diagonal distance is greater for a trench of given width.

Just filled levels in trenches of a given width as shown in FIG. 8result in trench corners and intersections being underfilled. Therefore,fill levels required must be based on the widest trench dimension foundin the trench configuration at the corners or intersections. It has alsobeen found that some over filling of trenches is desired to reduce localnon-polarities (cusp reduction).

A characteristic of the growth kinematics in the conformal regime isthat the linear rate of polysilicon as measured normal from thepolysilicon nucleating layer 44 is approximately constant and thepolysilicon refill is conformal and equal in thickness as measured fromthe vertical and horizontal trench surfaces. It is therefore importantto achieve the desired refill level while in the conformal regime. Voidsdo not form while in this conformal regime.

The data in FIG. 8 is employed to determine trench depths in whichconformal growth ensues for trenches of approximately 1-10 micrometersin width. It should be understood, however, that trenches of largerwidth such as up to 300 micrometers or greater, could be included withthe smaller width trenches on the same wafer since conformal growthwould also be occurring in these. The sidewall closure of such largewidth trenches would not occur prior to the smaller trenches beingadequately filled, and voids would not form.

FIG. 7 indicates the problem and solution namely first refillingpartially with void free epitaxial silicon as described above anddetermining from FIG. 8. the remaining portion to be filled withpolysilicon such that the initial cusp formation, along with theconcomitant ensueing rapid refill rates which incorporate voids areavoided.

FIG. 7 in addition schematically defines measurements and quantitiesdiscussed in the EXAMPLES shown below in FIG. 8 and attached TABLESwhich illustrate the utility of the data.

The following examples are included merely to aid in the understandingof the invention and variations may be made by one skilled in the artwithout departing from the spirit and scope of the invention.

EXAMPLE I

A mask set to form a series of trenches of the width indicated in theTABLE I was utilized to expose a photoresist layer which covered asilicon dioxide layer on a silicon substrate. Standard lithography andetching techniques were utilized to form this desired pattern in thesilicon dioxide layer. A reactive ion etching process was utilized whichincluded the use of CF₄ -H₂ to form a depth of trench as indicated inTABLE I for each of these trench widths. Polycrystalline silicon wasdeposited using an epitaxial AMC 7000 reactor manufactured by AppliedMaterials, Santa Clara, Calif., at atmospheric pressure. The reactor waspurged of air using first nitrogen gas and then hydrogen gas with theloaded wafers in the reactor. The reactor was heated to a temperature of1000° C. The reactant gas SiCl₄ and dopant B₂ H₆ were passed into thereactor with the SiCl₄ flow being 5 lpm (liters per minute) of H₂through SiCl₄ at 20 psig. (Bubbler at room temperature) and the B₂ H₆flow was 8.5 lpm of 60 ppm. The polysilicon deposition rate was about0.22 micrometers/minute. A resistivity of 0.003 ohm-cm. was obtained.The refilling process was continued 5 minutes. After the deposition, thereactor was purged with hydrogen and then nitrogen. The samples werecleaved through the trench sets having different width to obtain across-sectional view of the refills using scanning electron microscopic(SEM) techniques. Measurements were made from the photos to establishrefill rates in the trenches of various width and determine the refillcharacter. These measurements are given in the TABLE I.

EXAMPLE II

The identical process was utilized as described under EXAMPLE I but theprocess was continued for 10 minutes. Also, the trench width and trenchdepth are varied slightly from the EXAMPLE I trench width and trenchdepth and are given in TABLE II. The results of this process weremeasured as described in EXAMPLE I and the results of thesemeasurements.

EXAMPLE III

The process of EXAMPLE I was again repeated utilizing the trench widthand trench depth indicated in TABLE III and the process was continuedfor 15 minutes. The measurements of the resulting filled structures weremade according to the description of EXAMPLE I and have been listed inTABLE III.

EXAMPLE IV

The process of EXAMPLE III was again repeated utilizing the trench widthand trench depth indicated in TABLE IV and the process was continued for3.3 minutes. The measurements of the resulting filled structures weremade according to the description of EXAMPLE III and have been listed inTABLE IV.

EXAMPLE V

The process of EXAMPLE IV was again repeated utilizing the trench widthand trench depth indicated in TABLE V and the process was continued for6.6 minutes. The measurements of the resulting filled structures weremade according to the description of EXAMPLE IV and have been listed inTABLE V.

                                      TABLE I                                     __________________________________________________________________________    TRENCH REFILL KINEMATICS (5 MIN. RUN)                                         TRENCH                                                                              TRENCH                                                                              UNDERFILL (-) OR                                                                          GROWTH                                                                              CUSP CUSP TOTAL                                 WIDTH DEPTH OVERFILL (+)                                                                              IN FIELD                                                                            DEPTH                                                                              WIDTH                                                                              REFILL LEVEL                          (μm)                                                                             (μm)                                                                             (μm)     (μm)                                                                             (μm)                                                                            (μm)                                                                            (μm)                               __________________________________________________________________________    2.2   3.59   (+)0.242   0.96  0.87 2.2  3.63                                  3.3   3.59  (-)2.57     1.0   3.78 3.4  0.82                                  4.85  3.88  (-)2.62     1.16  3.98 5.0  1.06                                  7.45  3.86  (-)2.62     0.98  3.86 7.73 1.04                                  13.2  3.80  (-)2.48     1.12  3.80 12.5 1.12                                  24.7  3.80  (-)2.47     1.17  3.57 25.8 1.13                                  __________________________________________________________________________

                                      TABLE II                                    __________________________________________________________________________    TRENCH REFILL KINEMATICS (10 MIN. RUN)                                        TRENCH                                                                              TRENCH                                                                              UNDERFILL (-) OR                                                                          GROWTH                                                                              CUSP CUSP TOTAL                                 WIDTH DEPTH OVERFILL (+)                                                                              IN FIELD                                                                            DEPTH                                                                              WIDTH                                                                              REFILL LEVEL                          (μm)                                                                             (μm)                                                                             (μm)     (μm)                                                                             (μm)                                                                            (μm)                                                                            (μm)                               __________________________________________________________________________    2.44  3.66  (+)2.0      2.3   0.49 2.0  5.46                                  4.0   3.6   (+)1.38     2.2   0.9  3.4  4.78                                  4.9   3.7   (-)1.59     2.13  2.7  2.8  1.90                                  5.4   3.5   (-)1.43     1.8   3.5  4.2  1.87                                  7.46  3.98  (-)1.49     2.28  4.2  7.4  2.29                                  20.0  3.97  (-)1.49     2.12  5.6  20.8 2.28                                  __________________________________________________________________________

                                      TABLE III                                   __________________________________________________________________________    TRENCH REFILL KINEMATICS (15 MIN. RUN)                                        TRENCH                                                                              TRENCH                                                                              UNDERFILL (-) OR                                                                          GROWTH                                                                              CUSP CUSP TOTAL                                 WIDTH DEPTH OVERFILL (+)                                                                              IN FIELD                                                                            DEPTH                                                                              WIDTH                                                                              REFILL LEVEL                          (μm)                                                                             (μm)                                                                             (μm)     (μm)                                                                             (μm)                                                                            (μm)                                                                            (μm)                               __________________________________________________________________________    2.13  3.59  (+)3.0      3.2   0.6       6.39                                  3.49  3.59  (+)2.26     3.2   0.9  2.2  5.65                                  4.70  3.59  (+)1.8      3.2   1.74 3.48 5.19                                  7.25  3.6   (-)0.52     3.26       6.64 2.88                                  12.7  3.52              3.5                                                   24.0  3.13              3.52            2.9                                   __________________________________________________________________________

                  TABLE IV                                                        ______________________________________                                        TRENCH WIDTH    TOTAL REFILL                                                  (μm)         (μm)                                                       ______________________________________                                        1.36            4.5                                                           1.56            2.5                                                           1.7             1.3                                                           2.2             .7                                                            4.6             .8                                                            ______________________________________                                    

                  TABLE V                                                         ______________________________________                                        TRENCH WIDTH    TOTAL REFILL                                                  (μm)         (μm)                                                       ______________________________________                                        1.35            6.2                                                           1.7             5.8                                                           2.2              5.25                                                         2.8             3.0                                                           3.26            1.8                                                           3.28            1.3                                                           5.02            1.4                                                           ______________________________________                                    

The data obtained in the TABLES I-V was plotted in FIG. 8. Theelimination of the voids in the polysilicon refill is accomplished byremaining in the conformal growth regime as seen in FIG. 8. Theconditions for conformal growth is below the line 50 which may beexpressed by the equation y=0.34 x.

While the invention has been particularly shown and described withreference to the preferred embodiments thereof, it will be understood bythose skilled in the art that the foregoing and other changes in formand detail may be made therein without departing from the spirit andscope of the invention. For example, MOSFET devices may be formed withinthe isolation trench pattern rather than bipolar devices as described inthe principal examples herein. Where MOSFET, devices are used, theepitaxial layer may or may not be present as is understood by thoseskilled in the art. Where the epitaxial layer is not used, the depth ofthe isolation pattern may be reduced.

What is claimed is:
 1. A void free isolated semiconductor structurecomprising:a pattern of substantially vertically sided trenches within asemiconductor body; a first insulating layer upon the sidewalls of saidtrenches; combined void free epitaxial silicon and polycrystallinesilicon layers substantially located inside said trenches, said combinedsilicion layers comprising, an epitaxial layer extending from the baseof said trenches and filling said trenches up to between about 0.3 to4.0 micrometers from the upper surface of said trenches, said epitaxiallayer having a planar upper surface, said planar upper surface beingsubstantially parallel to said base of said trench, and apolycrystalline silicon layer over said planar upper surfaces of saidepitaxial layer; a second insulating layer covering the exposed uppersurface of said polycrystalline silicon layer and the exposed surfacesof said first insulating layer, isolating said pattern of trenches fromadjoining structures that exist over said trenches.
 2. The semiconductorstructure of claim 1 wherein the said semiconductor body ismonocrystalline silicon.
 3. The semiconductor structure of claim 1wherein said first insulating layer is composed of a silicon dioxidelayer and a silicon nitride layer.
 4. The semiconductor structure ofclaim 1 wherein a polycrystalline silicon nucleating layer is locatedupon said sidewalls in the area where said polycrystalline layer oversaid upper surfaces of said epitaxial layer is present.
 5. Thesemiconductor structure of claim 1 wherein the depth of said trenches isbetween about 3 to 10 micrometers.
 6. The semiconductor structure ofclaim 5 wherein the width of said trenches is between about 1 to 10micrometers.
 7. The semiconductor structure of claim 1 wherein saidsecond insulating layer is composed of a thermally grown silicondioxide.